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Pipelined implementations of the a priori error-feedback LSL algorithm using logarithmic arithmetic

Lookup NU author(s): Dr Nick Coleman

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Abstract

We present several implementations of the modified a priori error-feedback least square lattice (EF-LSL) algorithm (see Carezia, A. et al., ICASSP, p.921-4, 2001) on the Virtex FPGA. Its computational parallelism and pipelinability are important advantages. Internally, the computations are based on the logarithmic number system (LNS). We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solutions based on 32-bit floating-point processors. (11 References).

Publication metadata

Author(s): Coleman N; Albu F; Kadlec J; Fagan A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: International Conference on Acoustics, Speech, and Signal Processing (CASSP)

Year of Conference: 2002

Pages: 2681-2684

ISSN: 1520-6149

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ICASSP.2002.5745200

DOI: 10.1109/ICASSP.2002.5745200

Library holdings: Search Newcastle University Library for this item

ISBN: 0780374029

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