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Self-timed, Minimum Latency Circuits for the Internet of Things

Lookup NU author(s): Adrian WheeldonORCiD, Jordan Morris, Dr Danil Sokolov, Professor Alex YakovlevORCiD

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND).

Abstract

This work presents a design flow for asynchronous, self-timed dual-rail circuits which introduces a timing assumption in the return-to-spacer phase. The design flow enables power proportionality and is demonstrated through the design of a 32-bit ripple-carry adder and a 32-bit comparator for internet of things applications. The designs are synthesized to a 65nm cell library with state-of-the-art transistor sizing for subthreshold. Simulation results show improved performance and energy per computation across operating conditions compared with single-rail equivalents. The design flow allows extension of the power proportional philosophy to a wider range of circuits.

Publication metadata

Author(s): Wheeldon A, Morris J, Sokolov D, Yakovlev A

Publication type: Article

Publication status: Published

Journal: Integration

Year: 2019

Volume: 69

Pages: 138-146

Print publication date: 01/11/2019

Online publication date: 02/04/2019

Acceptance date: 28/01/2019

Date deposited: 23/02/2019

ISSN (print): 0167-9260

ISSN (electronic): 1872-7522

Publisher: Elsevier

URL: https://doi.org/10.1016/j.vlsi.2019.01.013

DOI: 10.1016/j.vlsi.2019.01.013

Data Access Statement: https://doi.org/10.17634/154300-111

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