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Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs

Lookup NU author(s): Asad Fayyaz, Dr Jesus Urresti IbanezORCiD, Professor Nick WrightORCiD

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Abstract

© 2017 IEEJ. This paper investigates the effect of negative gate bias voltage (Vgs) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

Publication metadata

Author(s): Fayyaz A, Castellazzi A, Romano G, Riccio M, Irace A, Urresti J, Wright N

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Proceedings of the 29th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2017

Year of Conference: 2017

Pages: 391-394

Online publication date: 24/07/2017

Acceptance date: 02/04/2016

Publisher: Institute of Electrical and Electronics Engineers Inc.

URL: https://doi.org/10.23919/ISPSD.2017.7988986

DOI: 10.23919/ISPSD.2017.7988986

Library holdings: Search Newcastle University Library for this item

ISBN: 9784886860958

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