A Heuristic Algorithm for Deriving Compact Models of Processor Instruction Sets

de, Gennaro, A; Stankaitis, P; Mokhov, A

doi:10.1109/ACSD.2015.17

A Heuristic Algorithm for Deriving Compact Models of Processor Instruction Sets

Lookup NU author(s): Alessandro De Gennaro, Gladys -, Dr Andrey Mokhov

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This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2015.

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Abstract

Finding a compact formal representation of a processor instruction set is important for easier comprehension by the designer, as well as for synthesis of an efficient hardware implementation of the processor's microcontroller.We present a new heuristic algorithm for deriving compact models of processor instruction sets. The algorithm is based on finding similarities between pairs of instructions and assigning similar opcodes (using a Hamming distance metric) to similar instructions (using a newly introduced instruction similarity metric). We demonstrate that this heuristic produces results with an average overhead, in terms of area, of 7.8\% in comparison to the global optimum on the benchmarks we studied (subsets of instructions of ARM Cortex M0+, Texas Instruments MSP430 and Intel 8051 processors).The algorithm is implemented as an open-source plugin for the Workcraft framework and is validated on a case study of a subset of 61 (out of 68) instructions of ARM Cortex M0+ processor. We compare the presented algorithm against a number of other available implementations.