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O. The trade-off between resolution time and delay times in bistable circuits

Lookup NU author(s): Mohammed Alshaikh, Professor David Kinniment, Professor Alex YakovlevORCiD

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Abstract

Flip flops used to store a bit in a register have different requirements to flip flops used in a synchronizer application. The D input must be held stable durin. The setup and unti. The Q output appears, these times determin. The remaining part oy the clock cycle available for computing. O. The other han. The D input can violate setup and hold times in a synchronizer, an. The reliability oy the synchronizer depends oy the metastability recovery time constant. We show how these parameters can be traded off in a simple edge triggered D flip flop and other cells. © 2009 IEEE.

Publication metadata

Author(s): Alshaikh M, Kinniment D, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Year of Conference: 2009

Pages: 355-358

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ICECS.2009.5410919

DOI: 10.1109/ICECS.2009.5410919

Library holdings: Search Newcastle University Library for this item

ISBN: 9781424450916

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