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An alternating spacer AES crypto-processor

Lookup NU author(s): Dr Julian Murphy, Professor Alex YakovlevORCiD

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Abstract

An AES crypto-processor has been fabricated to investigate the security properties of an alternating spacer dual-rail logic style and a security based design flow; which introduces a previously unused state in differential power-balancing. The fruits of which offer a tangible solution to information leakage during the life-time of a smartcard's secret key, whilst crucially keeping the usually expensive costs of increased smartcard security to a minimum: design economics, area and power. Power analysis on the device results in a forty fold increase in the number of power measurements needed to crack the 128-bit secret key over an unmodified and architecturally identical design. Area is only increased by 88% compared to 3-4x in other reported power-balancing methods [7], [8], [9].

Publication metadata

Author(s): Murphy J, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: ESSCIRC 2006: Proceedings of the 32nd European Solid-State Circuits Conference

Year of Conference: 2006

Pages: 126-129

ISSN: 1930-8833

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ESSCIR.2006.307547

DOI: 10.1109/ESSCIR.2006.307547

Library holdings: Search Newcastle University Library for this item

ISBN: 1424403030

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